Regviz

STMicroelectronics /STM32G071 /SYSCFG_VREFBUF /CFGR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFGR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32G07x/SYSCFG_VREFBUF/CFGR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MEM_MODE 0 (PA11_PA12_RMP)PA11_PA12_RMP 0 (IR_POL)IR_POL 0IR_MOD 0 (BOOSTEN)BOOSTEN 0 (UCPD1_STROBE)UCPD1_STROBE 0 (UCPD2_STROBE)UCPD2_STROBE 0I2C_PBx_FMP 0 (I2C1_FMP)I2C1_FMP 0 (I2C2_FMP)I2C2_FMP 0I2C_PAx_FMP

Description

SYSCFG configuration register 1

Fields

MEM_MODE

Memory mapping selection bits
PA11_PA12_RMP

PA11 and PA12 remapping bit.
IR_POL

IR output polarity selection
IR_MOD

IR Modulation Envelope signal selection.
BOOSTEN

I/O analog switch voltage booster enable
UCPD1_STROBE

Strobe signal bit for UCPD1
UCPD2_STROBE

Strobe signal bit for UCPD2
I2C_PBx_FMP

Fast Mode Plus (FM+) driving capability activation bits
I2C1_FMP

FM+ driving capability activation for I2C1
I2C2_FMP

FM+ driving capability activation for I2C2
I2C_PAx_FMP

Fast Mode Plus (FM+) driving capability activation bits

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data