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STMicroelectronics /STM32G071 /SYSCFG_VREFBUF /ITLINE17

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Interpret as ITLINE17

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM6)TIM6 0 (DAC)DAC 0 (LPTIM1)LPTIM1

Description

interrupt line 17 status register

Fields

TIM6

TIM6
DAC

DAC
LPTIM1

LPTIM1

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data