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STMicroelectronics /STM32G071 /TIM1 /OR1

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Interpret as OR1

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https://regviz.com/r/STMicroelectronics/STM32G070/TIM1/OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OCREF_CLR)OCREF_CLR

Description

option register 1

Fields

OCREF_CLR

Ocref_clr source selection

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data