ALERTEN=B_0x0, ANFOFF=B_0x0, ERRIE=B_0x0, NOSTRETCH=B_0x0, TXIE=B_0x0, TXDMAEN=B_0x0, RXDMAEN=B_0x0, RXIE=B_0x0, DNF=B_0x0, SMBDEN=B_0x0, TCIE=B_0x0, STOPIE=B_0x0, NACKIE=B_0x0, SBC=B_0x0, WUPEN=B_0x0, SMBHEN=B_0x0, PE=B_0x0, PECEN=B_0x0, ADDRIE=B_0x0, GCEN=B_0x0
Control register 1
| PE | Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. 0 (B_0x0): Peripheral disable 1 (B_0x1): Peripheral enable |
| TXIE | TX Interrupt enable 0 (B_0x0): Transmit (TXIS) interrupt disabled 1 (B_0x1): Transmit (TXIS) interrupt enabled |
| RXIE | RX Interrupt enable 0 (B_0x0): Receive (RXNE) interrupt disabled 1 (B_0x1): Receive (RXNE) interrupt enabled |
| ADDRIE | Address match Interrupt enable (slave only) 0 (B_0x0): Address match (ADDR) interrupts disabled 1 (B_0x1): Address match (ADDR) interrupts enabled |
| NACKIE | Not acknowledge received Interrupt enable 0 (B_0x0): Not acknowledge (NACKF) received interrupts disabled 1 (B_0x1): Not acknowledge (NACKF) received interrupts enabled |
| STOPIE | Stop detection Interrupt enable 0 (B_0x0): Stop detection (STOPF) interrupt disabled 1 (B_0x1): Stop detection (STOPF) interrupt enabled |
| TCIE | Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR) 0 (B_0x0): Transfer Complete interrupt disabled 1 (B_0x1): Transfer Complete interrupt enabled |
| ERRIE | Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT) 0 (B_0x0): Error detection interrupts disabled 1 (B_0x1): Error detection interrupts enabled |
| DNF | Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK … Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0). 0 (B_0x0): Digital filter disabled 1 (B_0x1): Digital filter enabled and filtering capability up to 1 tI2CCLK 15 (B_0xF): digital filter enabled and filtering capability up to15 tI2CCLK |
| ANFOFF | Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0). 0 (B_0x0): Analog noise filter enabled 1 (B_0x1): Analog noise filter disabled |
| TXDMAEN | DMA transmission requests enable 0 (B_0x0): DMA mode disabled for transmission 1 (B_0x1): DMA mode enabled for transmission |
| RXDMAEN | DMA reception requests enable 0 (B_0x0): DMA mode disabled for reception 1 (B_0x1): DMA mode enabled for reception |
| SBC | Slave byte control This bit is used to enable hardware byte control in slave mode. 0 (B_0x0): Slave byte control disabled 1 (B_0x1): Slave byte control enabled |
| NOSTRETCH | Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0). 0 (B_0x0): Clock stretching enabled 1 (B_0x1): Clock stretching disabled |
| WUPEN | Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â 0 (B_0x0): Wakeup from Stop mode disable. 1 (B_0x1): Wakeup from Stop mode enable. |
| GCEN | General call enable 0 (B_0x0): General call disabled. Address 0b00000000 is NACKed. 1 (B_0x1): General call enabled. Address 0b00000000 is ACKed. |
| SMBHEN | SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . 0 (B_0x0): Host Address disabled. Address 0b0001000x is NACKed. 1 (B_0x1): Host Address enabled. Address 0b0001000x is ACKed. |
| SMBDEN | SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . 0 (B_0x0): Device Default Address disabled. Address 0b1100001x is NACKed. 1 (B_0x1): Device Default Address enabled. Address 0b1100001x is ACKed. |
| ALERTEN | SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . 0 (B_0x0): The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK). 1 (B_0x1): The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK). |
| PECEN | PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . 0 (B_0x0): PEC calculation disabled 1 (B_0x1): PEC calculation enabled |