STMicroelectronics /STM32G0B0 /SPI1 /SPI_CR1

Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

0 (B_0x0): The first clock transition is the first data capture edge

1 (B_0x1): The second clock transition is the first data capture edge

Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

0 (B_0x0): CK to 0 when idle

1 (B_0x1): CK to 1 when idle

Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.

0 (B_0x0): Slave configuration

1 (B_0x1): Master configuration

Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.

0 (B_0x0): fPCLK/2

1 (B_0x1): fPCLK/4

2 (B_0x2): fPCLK/8

3 (B_0x3): fPCLK/16

4 (B_0x4): fPCLK/32

5 (B_0x5): fPCLK/64

6 (B_0x6): fPCLK/128

7 (B_0x7): fPCLK/256

SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1020. This bit is not used in I2S mode.

0 (B_0x0): Peripheral disabled

1 (B_0x1): Peripheral enabled

Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.

0 (B_0x0): data is transmitted / received with the MSB first

1 (B_0x1): data is transmitted / received with the LSB first

Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.

Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.

0 (B_0x0): Software slave management disabled

1 (B_0x1): Software slave management enabled

Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.

0 (B_0x0): Full-duplex (Transmit and receive)

1 (B_0x1): Output disabled (Receive-only mode)

CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = '0’) for correct operation. This bit is not used in I2S mode.

0 (B_0x0): 8-bit CRC length

1 (B_0x1): 16-bit CRC length

Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPIx_DR register. This bit is not used in I2S mode.

0 (B_0x0): Next transmit value is from Tx buffer.

1 (B_0x1): Next transmit value is from Tx CRC register.

Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = '0’) for correct operation. This bit is not used in I2S mode.

0 (B_0x0): CRC calculation disabled

1 (B_0x1): CRC calculation enabled

Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.

0 (B_0x0): Output disabled (receive-only mode)

1 (B_0x1): Output enabled (transmit-only mode)

Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.

0 (B_0x0): 2-line unidirectional data mode selected

1 (B_0x1): 1-line bidirectional data mode selected