DBG_TIM1_STOP=B_0x0, DBG_TIM15_STOP=B_0x0, DBG_TIM14_STOP=B_0x0, DBG_TIM17_STOP=B_0x0, DBG_TIM16_STOP=B_0x0
DBG APB freeze register 2
| DBG_TIM1_STOP | Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM14_STOP | Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM15_STOP | Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx. 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM16_STOP | Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM17_STOP | Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |