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STMicroelectronics /STM32G0B1 /PWR /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPMS0 (FPD_STOP)FPD_STOP 0 (FPD_LPRUN)FPD_LPRUN 0 (FPD_LPSLP)FPD_LPSLP 0 (DBP)DBP 0VOS0 (LPR)LPR

Description

Power control register 1

Fields

LPMS

Low-power mode selection
FPD_STOP

Flash memory powered down during Stop mode
FPD_LPRUN

Flash memory powered down during Low-power run mode
FPD_LPSLP

Flash memory powered down during Low-power sleep mode
DBP

Disable backup domain write protection
VOS

Voltage scaling range selection
LPR

Low-power run

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data