BKCMP2E=B_0x0, ETRSEL=B_0x0, BKINP=B_0x0, BKCMP2P=B_0x0, BKINE=B_0x0, BKCMP1P=B_0x0, BKCMP1E=B_0x0
DMA address for full transfer
| BKINE | BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): BKIN input disabled 1 (B_0x1): BKIN input enabled |
| BKCMP1E | BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): COMP1 input disabled 1 (B_0x1): COMP1 input enabled |
| BKCMP2E | BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): COMP2 input disabled 1 (B_0x1): COMP2 input enabled |
| BKINP | BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1) 1 (B_0x1): BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1) |
| BKCMP1P | BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1) 1 (B_0x1): COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1) |
| BKCMP2P | BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1) 1 (B_0x1): COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1) |
| ETRSEL | ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): ETR legacy mode 1 (B_0x1): COMP1 output 2 (B_0x2): COMP2 output 3 (B_0x3): ADC1 AWD1 4 (B_0x4): ADC1 AWD2 5 (B_0x5): ADC1 AWD3 |