BKF=B_0x0, OSSI=B_0x0, BKDSRM=B_0x0, BKP=B_0x0, OSSR=B_0x0, LOCK=B_0x0, AOE=B_0x0, MOE=B_0x0, BKBID=B_0x0, BKE=B_0x0
break and dead-time register
| DTG | Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). |
| LOCK | Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 0 (B_0x0): LOCK OFF - No bit is write protected 1 (B_0x1): LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 2 (B_0x2): LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 3 (B_0x3): LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. |
| OSSI | Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1 (B_0x1): When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) |
| OSSR | Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 1 (B_0x1): When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). |
| BKE | Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 0 (B_0x0): Break inputs (BRK and CCS clock failure event) disabled |
| BKP | Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 0 (B_0x0): Break input BRK is active low 1 (B_0x1): Break input BRK is active high |
| AOE | Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): MOE can be set only by software 1 (B_0x1): MOE can be set by software or automatically at the next update event (if the break input is not be active) |
| MOE | Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). 0 (B_0x0): OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1 (B_0x1): OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details ( |
| BKF | Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): No filter, BRK acts asynchronously 1 (B_0x1): fSAMPLING=fCK_INT, N=2 2 (B_0x2): fSAMPLING=fCK_INT, N=4 3 (B_0x3): fSAMPLING=fCK_INT, N=8 4 (B_0x4): fSAMPLING=fDTS/2, N=6 5 (B_0x5): fSAMPLING=fDTS/2, N=8 6 (B_0x6): fSAMPLING=fDTS/4, N=6 7 (B_0x7): fSAMPLING=fDTS/4, N=8 8 (B_0x8): fSAMPLING=fDTS/8, N=6 9 (B_0x9): fSAMPLING=fDTS/8, N=8 10 (B_0xA): fSAMPLING=fDTS/16, N=5 11 (B_0xB): fSAMPLING=fDTS/16, N=6 12 (B_0xC): fSAMPLING=fDTS/16, N=8 13 (B_0xD): fSAMPLING=fDTS/32, N=5 14 (B_0xE): fSAMPLING=fDTS/32, N=6 15 (B_0xF): fSAMPLING=fDTS/32, N=8 |
| BKDSRM | Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 0 (B_0x0): Break input BRK is armed 1 (B_0x1): Break input BRK is disarmed |
| BKBID | Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. 0 (B_0x0): Break input BRK in input mode 1 (B_0x1): Break input BRK in bidirectional mode |