STMicroelectronics /STM32G0B1 /USART1 /CR3

Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register).

0 (B_0x0): Interrupt inhibited

1 (B_0x1): interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.

IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): IrDA disabled

1 (B_0x1): IrDA enabled

IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): Normal mode

1 (B_0x1): Low-power mode

Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0).

0 (B_0x0): Half duplex mode is not selected

1 (B_0x1): Half duplex mode is selected

Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): NACK transmission in case of parity error is disabled

1 (B_0x1): NACK transmission during parity error is enabled

Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): Smartcard Mode disabled

1 (B_0x1): Smartcard Mode enabled

DMA enable receiver This bit is set/reset by software

0 (B_0x0): DMA mode is disabled for reception

1 (B_0x1): DMA mode is enabled for reception

DMA enable transmitter This bit is set/reset by software

0 (B_0x0): DMA mode is disabled for transmission

1 (B_0x1): DMA mode is enabled for transmission

RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): RTS hardware flow control disabled

1 (B_0x1): RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.

CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): CTS hardware flow control disabled

1 (B_0x1): CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.

CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): An interrupt is generated whenever CTSIF = 1 in the USART_ISR register

One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0).

0 (B_0x0): Three sample bit method

1 (B_0x1): One sample bit method

Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data

0 (B_0x0): Overrun Error Flag, ORE, is set when received data is not read before receiving new data.

1 (B_0x1): Overrun functionality is disabled. If new data is received while the RXNE flag is still set

DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.

0 (B_0x0): DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).

1 (B_0x1): DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.

Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .

0 (B_0x0): DE function is disabled.

1 (B_0x1): DE function is enabled. The DE signal is output on the RTS pin.

Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): DE signal is active high.

1 (B_0x1): DE signal is active low.

Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): retransmission disabled - No automatic retransmission in transmit mode.

1 (B_0x1): number of automatic retransmission attempts (before signaling error)

2 (B_0x2): number of automatic retransmission attempts (before signaling error)

3 (B_0x3): number of automatic retransmission attempts (before signaling error)

4 (B_0x4): number of automatic retransmission attempts (before signaling error)

5 (B_0x5): number of automatic retransmission attempts (before signaling error)

6 (B_0x6): number of automatic retransmission attempts (before signaling error)

7 (B_0x7): number of automatic retransmission attempts (before signaling error)

Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.

0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7)

2 (B_0x2): WUF active on start bit detection

3 (B_0x3): WUF active on RXNE/RXFNE.

Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever WUF = 1 in the USART_ISR register

TXFIFO threshold interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG.

Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever TCBGT=1 in the USART_ISR register

Receive FIFO threshold configuration Remaining combinations: Reserved

0 (B_0x0): Receive FIFO reaches 1/8 of its depth

1 (B_0x1): Receive FIFO reaches 1/4 of its depth

2 (B_0x2): Receive FIFO reaches 1/2 of its depth

3 (B_0x3): Receive FIFO reaches 3/4 of its depth

4 (B_0x4): Receive FIFO reaches 7/8 of its depth

5 (B_0x5): Receive FIFO becomes full

RXFIFO threshold interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG.

TXFIFO threshold configuration Remaining combinations: Reserved

0 (B_0x0): TXFIFO reaches 1/8 of its depth

1 (B_0x1): TXFIFO reaches 1/4 of its depth

2 (B_0x2): TXFIFO reaches 1/2 of its depth

3 (B_0x3): TXFIFO reaches 3/4 of its depth

4 (B_0x4): TXFIFO reaches 7/8 of its depth

5 (B_0x5): TXFIFO becomes empty