AWD3CH3=B_0x0, AWD3CH11=B_0x0, AWD3CH18=B_0x0, AWD3CH5=B_0x0, AWD3CH8=B_0x0, AWD3CH17=B_0x0, AWD3CH16=B_0x0, AWD3CH12=B_0x0, AWD3CH0=B_0x0, AWD3CH6=B_0x0, AWD3CH4=B_0x0, AWD3CH9=B_0x0, AWD3CH7=B_0x0, AWD3CH2=B_0x0, AWD3CH1=B_0x0, AWD3CH15=B_0x0, AWD3CH13=B_0x0, AWD3CH10=B_0x0, AWD3CH14=B_0x0
ADC Analog Watchdog 3 Configuration register
| AWD3CH0 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH1 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH2 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH3 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH4 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH5 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH6 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH7 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH8 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH9 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH10 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH11 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH12 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH13 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH14 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH15 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH16 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH17 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |
| AWD3CH18 | Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): ADC analog channel-x is not monitored by AWD3 1 (B_0x1): ADC analog channel-x is monitored by AWD3 |