PWRMODE=B_0x0, INPSEL=B_0x0, INMSEL=B_0x0, EN=B_0x0, HYST=B_0x0, POLARITY=B_0x0, WINMODE=B_0x0, BLANKSEL=B_0x0, WINOUT=B_0x0, LOCK=B_0x0
Comparator 1 control and status register
| EN | Comparator 1 enable bit This bit is controlled by software (if not locked). It enables the comparator 1: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| INMSEL | Comparator 1 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP1_INM of the comparator 1:
0 (B_0x0): 1/4 VREFINT 1 (B_0x1): 1/2 VREFINT 2 (B_0x2): 3/4 VREFINT 3 (B_0x3): VREFINT 4 (B_0x4): DAC channel 1 5 (B_0x5): DAC channel 2 6 (B_0x6): PB1 7 (B_0x7): PC4 8 (B_0x8): PA0 |
| INPSEL | Comparator 1 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP1_INP of the comparator 1 (also see the WINMODE bit): 0 (B_0x0): PC5 1 (B_0x1): PB2 2 (B_0x2): PA1 3 (B_0x3): None (open) |
| WINMODE | Comparator 1 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of the comparator 1: 0 (B_0x0): Signal selected with INPSEL[1:0] bitfield of this register 1 (B_0x1): COMP2_INP signal of the comparator 2 (required for window mode, see Figure 64) |
| WINOUT | Comparator 1 output selector This bit is controlled by software (if not locked). It selects the comparator 1 output: 0 (B_0x0): COMP1_VALUE 1 (B_0x1): COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 64) |
| POLARITY | Comparator 1 polarity selector This bit is controlled by software (if not locked). It selects the comparator 1 output polarity: 0 (B_0x0): Non-inverted 1 (B_0x1): Inverted |
| HYST | Comparator 1 hysteresis selector This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1: 0 (B_0x0): None 1 (B_0x1): Low 2 (B_0x2): Medium 3 (B_0x3): High |
| PWRMODE | Comparator 1 power mode selector This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1: others: Reserved 0 (B_0x0): High speed 1 (B_0x1): Medium speed |
| BLANKSEL | Comparator 1 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: xxxx1: TIM1 OC4 xxx1x: TIM1 OC5 xx1xx: TIM2 OC3 x1xxx: TIM3 OC3 1xxxx: TIM15 OC2 0 (B_0x0): None (no blanking) |
| VALUE | Comparator 1 output status This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in . |
| LOCK | COMP1_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 1 control register COMP1_CSR[31:0]: 0 (B_0x0): COMP1_CSR[31:0] register read/write bits can be written by software 1 (B_0x1): COMP1_CSR[31:0] register bits can be read but not written by software |