DBG_TIM2_STOP=B_0x0, DBG_WWDG_STOP=B_0x0, DBG_RTC_STOP=B_0x0, DBG_TIM6_STOP=B_0x0, DBG_TIM7_STOP=B_0x0, DBG_LPTIM2_STOP=B_0x0, DBG_LPTIM1_STOP=B_0x0, DBG_I2C1_SMBUS_TIMEOUT=B_0x0, DBG_IWDG_STOP=B_0x0, DBG_TIM3_STOP=B_0x0
DBG APB freeze register 1
| DBG_TIM2_STOP | Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM3_STOP | Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM6_STOP | Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_TIM7_STOP | Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_RTC_STOP | Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_WWDG_STOP | Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_IWDG_STOP | Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_I2C1_SMBUS_TIMEOUT | SMBUS timeout when core is halted 0 (B_0x0): Same behavior as in normal mode 1 (B_0x1): The SMBUS timeout is frozen |
| DBG_LPTIM2_STOP | Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |
| DBG_LPTIM1_STOP | Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted: 0 (B_0x0): Enable 1 (B_0x1): Disable |