STMicroelectronics /STM32G0C1 /DMAMUX /DMAMUX_C4CR

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Interpret as DMAMUX_C4CR

31282724232019161512118743000000000000000000000000000000000000000000DMAREQ_ID0 (B_0x0)SOIE0 (B_0x0)EGE0 (B_0x0)SE0 (B_0x0)SPOL0NBREQ0SYNC_ID

EGE=B_0x0, SPOL=B_0x0, SOIE=B_0x0, SE=B_0x0

Description

DMAMUX request line multiplexer channel x configuration register

Fields

DMAREQ_ID

DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.

SOIE

Synchronization overrun interrupt enable

0 (B_0x0): interrupt disabled

1 (B_0x1): interrupt enabled

EGE

Event generation enable

0 (B_0x0): event generation disabled

1 (B_0x1): event generation enabled

SE

Synchronization enable

0 (B_0x0): synchronization disabled

1 (B_0x1): synchronization enabled

SPOL

Synchronization polarity Defines the edge polarity of the selected synchronization input:

0 (B_0x0): no event, i.e. no synchronization nor detection.

1 (B_0x1): rising edge

2 (B_0x2): falling edge

3 (B_0x3): rising and falling edge

NBREQ

Number of DMA requests minus 1 to forward Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated. This field shall only be written when both SE and EGE bits are low.

SYNC_ID

Synchronization identification Selects the synchronization input (see inputs to resources STM32G0).

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