STMicroelectronics /STM32G0C1 /FDCAN1 /FDCAN_ECR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FDCAN_ECR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TEC0REC0 (B_0x0)RP 0CEL

RP=B_0x0

Description

FDCAN error counter register

Fields

TEC

Transmit error counter Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.

REC

Receive error counter Actual state of the receive error counter, values between 0 and 127.

RP

Receive error passive

0 (B_0x0): The receive error counter is below the error passive level of 128.

1 (B_0x1): The receive error counter has reached the error passive level of 128.

CEL

CAN error logging The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read.

Links

()