STMicroelectronics /STM32G0C1 /HDMI_CEC /CEC_CFGR

Signal free time SFT bits are set by software. In the SFT = 0x0 configuration, the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. 0x0 2.5 data-bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST = 1, TXERR = 1, TXUDR = 1 or TXACKE = 1) 4 data-bit periods if CEC is the new bus initiator 6 data-bit periods if CEC is the last bus initiator with successful transmission (TXEOM = 1)

1 (B_0x1): 0.5 nominal data bit periods

2 (B_0x2): 1.5 nominal data bit periods

3 (B_0x3): 2.5 nominal data bit periods

4 (B_0x4): 3.5 nominal data bit periods

5 (B_0x5): 4.5 nominal data bit periods

6 (B_0x6): 5.5 nominal data bit periods

7 (B_0x7): 6.5 nominal data bit periods

Rx-tolerance The RXTOL bit is set and cleared by software. Start-bit, +/- 200 µs rise, +/- 200 µs fall Data-bit: +/- 200 µs rise. +/- 350 µs fall Start-bit: +/- 400 µs rise, +/- 400 µs fall Data-bit: +/-300 µs rise, +/- 500 µs fall

0 (B_0x0): Standard tolerance margin:

1 (B_0x1): Extended tolerance

Rx-stop on bit rising error The BRESTP bit is set and cleared by software.

0 (B_0x0): BRE detection does not stop reception of the CEC message. Data bit is sampled at 1.05 ms.

1 (B_0x1): BRE detection stops message reception.

Generate error-bit on bit rising error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon BRE detection with BRESTP = 1 in broadcast even if BREGEN = 0.

0 (B_0x0): BRE detection does not generate an error-bit on the CEC line.

1 (B_0x1): BRE detection generates an error-bit on the CEC line (if BRESTP is set).

Generate error-bit on long bit period error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon LBPE detection in broadcast even if LBPEGEN = 0.

0 (B_0x0): LBPE detection does not generate an error-bit on the CEC line.

1 (B_0x1): LBPE detection generates an error-bit on the CEC line.

Avoid error-bit generation in broadcast The BRDNOGEN bit is set and cleared by software. error-bit on the CEC line. LBPE detection with LBPEGEN = 0 on a broadcast message generates an error-bit on the CEC line.

0 (B_0x0): BRE detection with BRESTP = 1 and BREGEN = 0 on a broadcast message generates an

1 (B_0x1): Error-bit is not generated in the same condition as above. An error-bit is not generated even in case of an SBPE detection in a broadcast message if listen mode is set.

SFT option bit The SFTOPT bit is set and cleared by software.

0 (B_0x0): SFT timer starts when TXSOM is set by software.

1 (B_0x1): SFT timer starts automatically at the end of message transmission/reception.

Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN = 1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.

Listen mode LSTN bit is set and cleared by software.

0 (B_0x0): CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.

1 (B_0x1): CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.