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STMicroelectronics /STM32G0C1 /LPTIM1 /LPTIM_CFGR2

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Interpret as LPTIM_CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IN1SEL 0 (B_0x0)IN2SEL

IN2SEL=B_0x0, IN1SEL=B_0x0

Description

LPTIM configuration register 2

Fields

IN1SEL

LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to .

0 (B_0x0): lptim_in1_mux0

1 (B_0x1): lptim_in1_mux1

2 (B_0x2): lptim_in1_mux2

3 (B_0x3): lptim_in1_mux3
IN2SEL

LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to .

0 (B_0x0): lptim_in2_mux0

1 (B_0x1): lptim_in2_mux1

2 (B_0x2): lptim_in2_mux2

3 (B_0x3): lptim_in2_mux3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data