STMicroelectronics /STM32G0C1 /LPTIM1 /LPTIM_IER

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Interpret as LPTIM_IER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CMPMIE 0 (B_0x0)ARRMIE 0 (B_0x0)EXTTRIGIE 0 (B_0x0)CMPOKIE 0 (B_0x0)ARROKIE 0 (B_0x0)UPIE 0 (B_0x0)DOWNIE

ARRMIE=B_0x0, UPIE=B_0x0, ARROKIE=B_0x0, CMPMIE=B_0x0, DOWNIE=B_0x0, CMPOKIE=B_0x0, EXTTRIGIE=B_0x0

Description

Interrupt Enable Register

Fields

CMPMIE

Compare match Interrupt Enable

0 (B_0x0): CMPM interrupt disabled

1 (B_0x1): CMPM interrupt enabled

ARRMIE

Autoreload match Interrupt Enable

0 (B_0x0): ARRM interrupt disabled

1 (B_0x1): ARRM interrupt enabled

EXTTRIGIE

External trigger valid edge Interrupt Enable

0 (B_0x0): EXTTRIG interrupt disabled

1 (B_0x1): EXTTRIG interrupt enabled

CMPOKIE

Compare register update OK Interrupt Enable

0 (B_0x0): CMPOK interrupt disabled

1 (B_0x1): CMPOK interrupt enabled

ARROKIE

Autoreload register update OK Interrupt Enable

0 (B_0x0): ARROK interrupt disabled

1 (B_0x1): ARROK interrupt enabled

UPIE

Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .

0 (B_0x0): UP interrupt disabled

1 (B_0x1): UP interrupt enabled

DOWNIE

Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to .

0 (B_0x0): DOWN interrupt disabled

1 (B_0x1): DOWN interrupt enabled

Links

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