STMicroelectronics /STM32G0C1 /RCC /CICR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CICR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYC)LSIRDYC 0 (LSERDYC)LSERDYC 0 (HSI48RDYC)HSI48RDYC 0 (HSIRDYC)HSIRDYC 0 (HSERDYC)HSERDYC 0 (PLLSYSRDYC)PLLSYSRDYC 0 (CSSC)CSSC 0 (LSECSSC)LSECSSC

Description

Clock interrupt clear register

Fields

LSIRDYC

LSI ready interrupt clear

LSERDYC

LSE ready interrupt clear

HSI48RDYC

HSI48RDYC

HSIRDYC

HSI ready interrupt clear

HSERDYC

HSE ready interrupt clear

PLLSYSRDYC

PLL ready interrupt clear

CSSC

Clock security system interrupt clear

LSECSSC

LSE Clock security system interrupt clear

Links

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