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STMicroelectronics /STM32G0C1 /TIM1 /CCMR3_Output

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Interpret as CCMR3_Output

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OC5FE)OC5FE 0 (OC5PE)OC5PE 0OC5M0 (OC5CE)OC5CE 0 (OC6FE)OC6FE 0 (OC6PE)OC6PE 0OC6M0 (OC6CE)OC6CE 0 (OC5M_bit3)OC5M_bit3 0 (OC6M_bit3)OC6M_bit3

Description

capture/compare mode register 2 (output mode)

Fields

OC5FE

Output compare 5 fast enable
OC5PE

Output compare 5 preload enable
OC5M

Output compare 5 mode
OC5CE

Output compare 5 clear enable
OC6FE

Output compare 6 fast enable
OC6PE

Output compare 6 preload enable
OC6M

Output compare 6 mode
OC6CE

Output compare 6 clear enable
OC5M_bit3

Output Compare 5 mode bit 3
OC6M_bit3

Output Compare 6 mode bit 3

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data