CC1IF=B_0x0, CC1OF=B_0x0, UIF=B_0x0
status register
| UIF | Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=â0â in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=â0â and UDIS=â0â in the TIMx_CR1 register. 0 (B_0x0): No update occurred. 1 (B_0x1): Update interrupt pending. This bit is set by hardware when the registers are updated: |
| CC1IF | Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER). 0 (B_0x0): No compare match / No input capture occurred 1 (B_0x1): A compare match or an input capture occurred. |
| CC1OF | Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â. 0 (B_0x0): No overcapture has been detected. 1 (B_0x1): The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set |