UIFREMAP=B_0x0, ARPE=B_0x0, OPM=B_0x0, URS=B_0x0, DIR=B_0x0, UDIS=B_0x0, CKD=B_0x0, CEN=B_0x0, CMS=B_0x0
control register 1
| CEN | Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 0 (B_0x0): UEV enabled. The Update (UEV) event is generated by one of the following events: 1 (B_0x1): UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. |
| URS | Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 0 (B_0x0): Any of the following events generate an update interrupt or DMA request if enabled. These events can be: 1 (B_0x1): Only counter overflow/underflow generates an update interrupt or DMA request if enabled. |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped at update event 1 (B_0x1): Counter stops counting at the next update event (clearing the bit CEN) |
| DIR | Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. 0 (B_0x0): Counter used as upcounter 1 (B_0x1): Counter used as downcounter |
| CMS | Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) 0 (B_0x0): Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 1 (B_0x1): Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 2 (B_0x2): Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 3 (B_0x3): Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIMx_ARR register is not buffered 1 (B_0x1): TIMx_ARR register is buffered |
| CKD | Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 0 (B_0x0): tDTS = tCK_INT 1 (B_0x1): tDTS = 2 Ã tCK_INT 2 (B_0x2): tDTS = 4 Ã tCK_INT |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. 1 (B_0x1): Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. |