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STMicroelectronics /STM32G0C1 /UCPD1 /UCPD_CFGR2

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Interpret as UCPD_CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RXFILTDIS 0 (B_0x0)RXFILT2N3 0 (B_0x0)FORCECLK 0 (B_0x0)WUPEN

RXFILT2N3=B_0x0, WUPEN=B_0x0, RXFILTDIS=B_0x0, FORCECLK=B_0x0

Description

UCPD configuration register 2

Fields

RXFILTDIS

BMC decoder Rx pre-filter enable The sampling clock is that of the receiver (that is, after pre-scaler).

0 (B_0x0): Enable

1 (B_0x1): Disable
RXFILT2N3

BMC decoder Rx pre-filter sampling method Number of consistent consecutive samples before confirming a new value.

0 (B_0x0): 3 samples

1 (B_0x1): 2 samples
FORCECLK

Force ClkReq clock request

0 (B_0x0): Do not force clock request

1 (B_0x1): Force clock request
WUPEN

Wakeup from Stop mode enable Setting the bit enables the UCPD_ASYNC_INT signal.

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data