DBATTEN=B_0x0, CC1VCONNEN=B_0x0, ANAMODE=B_0x0, RXMODE=B_0x0, CC2TCDIS=B_0x0, CC2VCONNEN=B_0x0, PHYRXEN=B_0x0, RDCH=B_0x0, FRSTX=B_0x0, TXHRST=B_0x0, TXMODE=B_0x0, PHYCCSEL=B_0x0, CC1TCDIS=B_0x0, TXSEND=B_0x0, CCENABLE=B_0x0
UCPD control register
| TXMODE | Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the “tBISTContMode” delay), disable the peripheral (UCPDEN = 0). 0 (B_0x0): Transmission of Tx packet previously defined in other registers 1 (B_0x1): Cable Reset sequence 2 (B_0x2): BIST test sequence (BIST Carrier Mode 2) |
| TXSEND | Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded. 0 (B_0x0): No effect 1 (B_0x1): Start Tx packet transmission |
| TXHRST | Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded. 0 (B_0x0): No effect 1 (B_0x1): Start Tx Hard Reset message |
| RXMODE | Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message. 0 (B_0x0): Normal receive mode 1 (B_0x1): BIST receive mode (BIST test data mode) |
| PHYRXEN | USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PHYCCSEL | CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach. 0 (B_0x0): Use CC1 IO for Power Delivery communication 1 (B_0x1): Use CC2 IO for Power Delivery communication |
| ANASUBMODE | Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield. |
| ANAMODE | Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]. 0 (B_0x0): Source 1 (B_0x1): Sink |
| CCENABLE | CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source. 0 (B_0x0): Disable both PHYs 1 (B_0x1): Enable CC1 PHY 2 (B_0x2): Enable CC2 PHY 3 (B_0x3): Enable CC1 and CC2 PHY |
| CC1VCONNEN | VCONN switch enable for CC1 0 (B_0x0): Disable 1 (B_0x1): Enable |
| CC2VCONNEN | VCONN switch enable for CC2 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DBATTEN | Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| FRSRXEN | FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink. 1 (B_0x1): Enable |
| FRSTX | FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0. 0 (B_0x0): No effect 1 (B_0x1): Enable |
| RDCH | Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to “USB Type-C ECN for Source VCONN Discharge”. The CCENABLE[1:0] bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register. 0 (B_0x0): No effect 1 (B_0x1): Rdch condition drive |
| CC1TCDIS | CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0]. 0 (B_0x0): Enable 1 (B_0x1): Disable |
| CC2TCDIS | CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0]. 0 (B_0x0): Enable 1 (B_0x1): Disable |