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STMicroelectronics /STM32G0C1 /UCPD1 /UCPD_RX_ORDSETR

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Interpret as UCPD_RX_ORDSETR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RXORDSET 0 (B_0x0)RXSOP3OF4 0 (B_0x0)RXSOPKINVALID

RXORDSET=B_0x0, RXSOPKINVALID=B_0x0, RXSOP3OF4=B_0x0

Description

UCPD Rx ordered set register

Fields

RXORDSET

Rx ordered set code detected

0 (B_0x0): SOP code detected in receiver

1 (B_0x1): SOP’ code detected in receiver

2 (B_0x2): SOP’’ code detected in receiver

3 (B_0x3): SOP’_Debug detected in receiver

4 (B_0x4): SOP’'_Debug detected in receiver

5 (B_0x5): Cable Reset detected in receiver

6 (B_0x6): SOP extension#1 detected in receiver

7 (B_0x7): SOP extension#2 detected in receiver
RXSOP3OF4

The bit indicates the number of correct K‑codes. For debug purposes only.

0 (B_0x0): 4 correct K‑codes out of 4‑

1 (B_0x1): 3 correct K‑codes out of 4‑
RXSOPKINVALID

The bitfield is for debug purposes only. Others: Invalid

0 (B_0x0): No K‑code corrupted

1 (B_0x1): First K‑code corrupted

2 (B_0x2): Second K‑code corrupted

3 (B_0x3): Third K‑code corrupted

4 (B_0x4): Fourth K‑code corrupted

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data