STMicroelectronics /STM32G431xx /DAC1 /DAC_SWTRGR

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Interpret as DAC_SWTRGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWTRIG1)SWTRIG1 0 (SWTRIG2)SWTRIG2 0 (SWTRIGB1)SWTRIGB1 0 (SWTRIGB2)SWTRIGB2

Description

DAC software trigger register

Fields

SWTRIG1

DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.

SWTRIG2

DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.

SWTRIGB1

DAC channel1 software trigger B

SWTRIGB2

DAC channel2 software trigger B

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