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STMicroelectronics /STM32G431xx /FDCAN /ILE

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Interpret as ILE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EINT0)EINT0 0 (EINT1)EINT1

Description

Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.

Fields

EINT0

EINT0
EINT1

EINT1

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data