ADC12EN=B_0x0, AESEN=B_0x0, GPIOGEN=B_0x0, ADC345EN=B_0x0, RNGEN=B_0x0, GPIOFEN=B_0x0, DAC1EN=B_0x0, DAC4EN=B_0x0, GPIODEN=B_0x0, GPIOCEN=B_0x0, DAC3EN=B_0x0, DAC2EN=B_0x0, GPIOBEN=B_0x0, GPIOAEN=B_0x0, GPIOEEN=B_0x0
AHB2 peripheral clock enable register
| GPIOAEN | IO port A clock enable Set and cleared by software. 0 (B_0x0): IO port A clock disabled 1 (B_0x1): IO port A clock enabled |
| GPIOBEN | IO port B clock enable Set and cleared by software. 0 (B_0x0): IO port B clock disabled 1 (B_0x1): IO port B clock enabled |
| GPIOCEN | IO port C clock enable Set and cleared by software. 0 (B_0x0): IO port C clock disabled 1 (B_0x1): IO port C clock enabled |
| GPIODEN | IO port D clock enable Set and cleared by software. 0 (B_0x0): IO port D clock disabled 1 (B_0x1): IO port D clock enabled |
| GPIOEEN | IO port E clock enable Set and cleared by software. 0 (B_0x0): IO port E clock disabled 1 (B_0x1): IO port E clock enabled |
| GPIOFEN | IO port F clock enable Set and cleared by software. 0 (B_0x0): IO port F clock disabled 1 (B_0x1): IO port F clock enabled |
| GPIOGEN | IO port G clock enable Set and cleared by software. 0 (B_0x0): IO port G clock disabled 1 (B_0x1): IO port G clock enabled |
| ADC12EN | ADC12 clock enable Set and cleared by software. 0 (B_0x0): ADC12 clock disabled 1 (B_0x1): ADC12 clock enabled |
| ADC345EN | ADC345 clock enable Set and cleared by software 0 (B_0x0): ADC345 clock disabled 1 (B_0x1): ADC345 clock enabled |
| DAC1EN | DAC1 clock enable Set and cleared by software. 0 (B_0x0): DAC1 clock disabled 1 (B_0x1): DAC1 clock enabled |
| DAC2EN | DAC2 clock enable Set and cleared by software. 0 (B_0x0): DAC2 clock disabled 1 (B_0x1): DAC2 clock enabled |
| DAC3EN | DAC3 clock enable Set and cleared by software. 0 (B_0x0): DAC3 clock disabled 1 (B_0x1): DAC3 clock enabled |
| DAC4EN | DAC4 clock enable Set and cleared by software. 0 (B_0x0): DAC4 clock disabled 1 (B_0x1): DAC4 clock enabled |
| AESEN | AES clock enable Set and cleared by software. 0 (B_0x0): AES clock disabled 1 (B_0x1): AES clock enabled |
| RNGEN | RNG enable Set and cleared by software. 0 (B_0x0): RNG disabled 1 (B_0x1): RNG enabled |