RegViz: Visualize RCC_CCIPR Bitfield

STMicroelectronics /STM32G431xx /RCC /RCC_CCIPR

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Interpret as RCC_CCIPR

I2C3SEL=B_0x0, USART2SEL=B_0x0, ADC345SEL=B_0x0, SAI1SEL=B_0x0, I2C1SEL=B_0x0, USART1SEL=B_0x0, LPTIM1SEL=B_0x0, UART4SEL=B_0x0, LPUART1SEL=B_0x0, ADC12SEL=B_0x0, UART5SEL=B_0x0, USART3SEL=B_0x0, I2S23SEL=B_0x0, I2C2SEL=B_0x0, CLK48SEL=B_0x0

Description

Peripherals independent clock configuration register

Fields

USART1SEL	USART1 clock source selection This bit is set and cleared by software to select the USART1 clock source. 0 (B_0x0): PCLK selected as USART1 clock 1 (B_0x1): System clock (SYSCLK) selected as USART1 clock 2 (B_0x2): HSI16 clock selected as USART1 clock 3 (B_0x3): LSE clock selected as USART1 clock
USART2SEL	USART2 clock source selection This bit is set and cleared by software to select the USART2 clock source. 0 (B_0x0): PCLK selected as USART2 clock 1 (B_0x1): System clock (SYSCLK) selected as USART2 clock 2 (B_0x2): HSI16 clock selected as USART2 clock 3 (B_0x3): LSE clock selected as USART2 clock
USART3SEL	USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 0 (B_0x0): PCLK selected as USART3 clock 1 (B_0x1): System clock (SYSCLK) selected as USART3 clock 2 (B_0x2): HSI16 clock selected as USART3 clock 3 (B_0x3): LSE clock selected as USART3 clock
UART4SEL	UART4 clock source selection This bit is set and cleared by software to select the UART4 clock source. 0 (B_0x0): PCLK selected as UART4 clock 1 (B_0x1): System clock (SYSCLK) selected as UART4 clock 2 (B_0x2): HSI16 clock selected as UART4 clock 3 (B_0x3): LSE clock selected as UART4 clock
UART5SEL	UART5 clock source selection These bits are set and cleared by software to select the UART5 clock source. 0 (B_0x0): PCLK selected as UART5 clock 1 (B_0x1): System clock (SYSCLK) selected as UART5 clock 2 (B_0x2): HSI16 clock selected as UART5 clock 3 (B_0x3): LSE clock selected as UART5 clock
LPUART1SEL	LPUART1 clock source selection These bits are set and cleared by software to select the LPUART1 clock source. 0 (B_0x0): PCLK selected as LPUART1 clock 1 (B_0x1): System clock (SYSCLK) selected as LPUART1 clock 2 (B_0x2): HSI16 clock selected as LPUART1 clock 3 (B_0x3): LSE clock selected as LPUART1 clock
I2C1SEL	I2C1 clock source selection These bits are set and cleared by software to select the I2C1 clock source. 0 (B_0x0): PCLK selected as I2C1 clock 1 (B_0x1): System clock (SYSCLK) selected as I2C1 clock 2 (B_0x2): HSI16 clock selected as I2C1 clock 3 (B_0x3): Reserved
I2C2SEL	I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source. 0 (B_0x0): PCLK selected as I2C2 clock 1 (B_0x1): System clock (SYSCLK) selected as I2C2 clock 2 (B_0x2): HSI16 clock selected as I2C2 clock 3 (B_0x3): Reserved
I2C3SEL	I2C3 clock source selection These bits are set and cleared by software to select the I2C3 clock source. 0 (B_0x0): PCLK selected as I2C3 clock 1 (B_0x1): System clock (SYSCLK) selected as I2C3 clock 2 (B_0x2): HSI16 clock selected as I2C3 clock 3 (B_0x3): Reserved
LPTIM1SEL	Low power timer 1 clock source selection These bits are set and cleared by software to select the LPTIM1 clock source. 0 (B_0x0): PCLK selected as LPTIM1 clock 1 (B_0x1): LSI clock selected as LPTIM1 clock 2 (B_0x2): HSI16 clock selected as LPTIM1 clock 3 (B_0x3): LSE clock selected as LPTIM1 clock
SAI1SEL	clock source selection These bits are set and cleared by software to select the SAI clock source. 0 (B_0x0): System clock selected as SAI clock 1 (B_0x1): PLL “Q” clock selected as SAI clock 2 (B_0x2): Clock provided on I2S_CKIN pin selected as SAI clock 3 (B_0x3): HSI16 clock selected as SAI clock
I2S23SEL	clock source selection These bits are set and cleared by software to select the I2S23 clock source. 0 (B_0x0): System clock selected as I2S23 clock 1 (B_0x1): PLL “Q” clock selected as I2S23 clock 2 (B_0x2): Clock provided on I2S_CKIN pin is selected as I2S23 clock 3 (B_0x3): HSI16 clock selected as I2S23 clock.
FDCANSEL	None
CLK48SEL	48 MHz clock source selection These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG. 0 (B_0x0): HSI48 clock selected as 48 MHz clock 1 (B_0x1): Reserved 2 (B_0x2): PLL “Q” clock (PLL48M1CLK) selected as 48 MHz clock 3 (B_0x3): Reserved, must be kept at reset value
ADC12SEL	ADC1/2 clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface. 0 (B_0x0): No clock selected 1 (B_0x1): PLL “P” clock selected as ADC1/2 clock 2 (B_0x2): System clock selected as ADC1/2 clock 3 (B_0x3): Reserved
ADC345SEL	ADC3/4/5 clock source selection These bits are set and cleared by software to select the clock source used by the ADC345 interface. 0 (B_0x0): No clock selected 1 (B_0x1): PLL “P” clock selected as ADC345 clock 2 (B_0x2): System clock selected as ADC3/4/5 clock 3 (B_0x3): Reserved.

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