The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
| RF0N | RF0N |
| RF0F | RF0F |
| RF0L | RF0L |
| RF1N | RF1N |
| RF1F | RF1F |
| RF1L | RF1L |
| HPM | HPM |
| TC | TC |
| TCF | TCF |
| TFE | TFE |
| TEFN | TEFN |
| TEFF | TEFF |
| TEFL | TEFL |
| TSW | TSW |
| MRAF | MRAF |
| TOO | TOO |
| ELO | ELO |
| EP | EP |
| EW | EW |
| BO | BO |
| WDI | WDI |
| PEA | PEA |
| PED | PED |
| ARA | ARA |