HSIKERON=B_0x0, PLLON=B_0x0, HSIRDY=B_0x0, PLLRDY=B_0x0, CSSON=B_0x0, HSEON=B_0x0, HSEBYP=B_0x0, HSERDY=B_0x0, HSION=B_0x0
Clock control register
| HSION | HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 0 (B_0x0): HSI16 oscillator OFF 1 (B_0x1): HSI16 oscillator ON |
| HSIKERON | HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 0 (B_0x0): No effect on HSI16 oscillator. 1 (B_0x1): HSI16 oscillator is forced ON even in Stop mode. |
| HSIRDY | HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. 0 (B_0x0): HSI16 oscillator not ready 1 (B_0x1): HSI16 oscillator ready |
| HSEON | HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0 (B_0x0): HSE oscillator OFF 1 (B_0x1): HSE oscillator ON |
| HSERDY | HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. 0 (B_0x0): HSE oscillator not ready 1 (B_0x1): HSE oscillator ready |
| HSEBYP | HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0 (B_0x0): HSE crystal oscillator not bypassed 1 (B_0x1): HSE crystal oscillator bypassed with external clock |
| CSSON | Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 0 (B_0x0): Clock security system OFF (clock detector OFF) 1 (B_0x1): Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). |
| PLLON | Main PLL enable Set and cleared by software to enable the main PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. 0 (B_0x0): PLL OFF 1 (B_0x1): PLL ON |
| PLLRDY | Main PLL clock ready flag Set by hardware to indicate that the main PLL is locked. 0 (B_0x0): PLL unlocked 1 (B_0x1): PLL locked |