STMicroelectronics /STM32G483xx /FDCAN /IE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RF0NE)RF0NE 0 (RF0FE)RF0FE 0 (RF0LE)RF0LE 0 (RF1NE)RF1NE 0 (RF1FE)RF1FE 0 (RF1LE)RF1LE 0 (HPME)HPME 0 (TCE)TCE 0 (TCFE)TCFE 0 (TFEE)TFEE 0 (TEFNE)TEFNE 0 (TEFFE)TEFFE 0 (TEFLE)TEFLE 0 (TSWE)TSWE 0 (MRAFE)MRAFE 0 (TOOE)TOOE 0 (ELOE)ELOE 0 (EPE)EPE 0 (EWE)EWE 0 (BOE)BOE 0 (WDIE)WDIE 0 (PEAE)PEAE 0 (PEDE)PEDE 0 (ARAE)ARAE

Description

The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.

Fields

RF0NE

RF0NE

RF0FE

RF0FE

RF0LE

RF0LE

RF1NE

RF1NE

RF1FE

RF1FE

RF1LE

RF1LE

HPME

HPME

TCE

TCE

TCFE

TCFE

TFEE

TFEE

TEFNE

TEFNE

TEFFE

TEFFE

TEFLE

TEFLE

TSWE

TSWE

MRAFE

MRAFE

TOOE

TOOE

ELOE

ELOE

EPE

EPE

EWE

EWE

BOE

BOE

WDIE

WDIE

PEAE

PEAE

PEDE

PEDE

ARAE

ARAE

Links

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