STMicroelectronics /STM32G483xx /PWR /PWR_CR3

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Interpret as PWR_CR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EWUP1)EWUP1 0 (EWUP2)EWUP2 0 (EWUP3)EWUP3 0 (EWUP4)EWUP4 0 (EWUP5)EWUP5 0 (B_0x0)RRS 0 (APC)APC 0 (B_0x0)UCPD1_STDBY 0 (B_0x0)UCPD1_DBDIS 0 (B_0x0)EIWUL

UCPD1_STDBY=B_0x0, UCPD1_DBDIS=B_0x0, EIWUL=B_0x0, RRS=B_0x0

Description

Power control register 3

Fields

EWUP1

Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register.

EWUP2

Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register.

EWUP3

Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.

EWUP4

Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.

EWUP5

Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register.

RRS

SRAM2 retention in Standby mode

0 (B_0x0): SRAM2 is powered off in Standby mode (SRAM2 content is lost).

1 (B_0x1): SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept).

APC

Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.

UCPD1_STDBY

UCPD1_STDBY USB Type-C and Power Delivery standby mode.

0 (B_0x0): Write ‘0’ immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers).

1 (B_0x1): Write ‘1’ just before entering standby when using UCPD1.

UCPD1_DBDIS

USB Type-C and Power Delivery Dead Battery disable. After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to hand over control to the UCPD1 (which should therefore be initialized before doing the disable).

0 (B_0x0): Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins.

1 (B_0x1): Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins.

EIWUL

Enable internal wakeup line

0 (B_0x0): Internal wakeup line disable.

1 (B_0x1): Internal wakeup line enable.

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