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STMicroelectronics /STM32G483xx /PWR /PWR_SCR

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Interpret as PWR_SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CWUF1)CWUF1 0 (CWUF2)CWUF2 0 (CWUF3)CWUF3 0 (CWUF4)CWUF4 0 (CWUF5)CWUF5 0 (CSBF)CSBF

Description

Power status clear register

Fields

CWUF1

Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
CWUF2

Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register.
CWUF3

Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register.
CWUF4

Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register.
CWUF5

Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register.
CSBF

Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data