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STMicroelectronics /STM32G484xx /HRTIM_TIMA /TIMACR2

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Interpret as TIMACR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DCDE)DCDE 0 (DCDS)DCDS 0 (DCDR)DCDR 0 (UDM)UDM 0ROM0OUTROM 0ADROM 0BMROM 0FEROM 0 (GTCMP1)GTCMP1 0 (GTCMP3)GTCMP3 0 (TRGHLF)TRGHLF

Description

HRTIM Timerx Control Register 2

Fields

DCDE

Dual Channel DAC trigger enable
DCDS

Dual Channel DAC Step trigger
DCDR

Dual Channel DAC Reset trigger
UDM

Up-Down Mode
ROM

Roll-Over Mode
OUTROM

Output Roll-Over Mode
ADROM

ADC Roll-Over Mode
BMROM

Burst Mode Roll-Over Mode
FEROM

Fault and Event Roll-Over Mode
GTCMP1

Greater than Compare 1 PWM mode
GTCMP3

Greater than Compare 3 PWM mode
TRGHLF

Triggered-half mode

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data