STMicroelectronics /STM32G484xx /HRTIM_TIMC /SETC1R

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Interpret as SETC1R

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SST)SST 0 (RESYNC)RESYNC 0 (PER)PER 0 (CMP1)CMP1 0 (CMP2)CMP2 0 (CMP3)CMP3 0 (CMP4)CMP4 0 (MSTPER)MSTPER 0 (MSTCMP1)MSTCMP1 0 (MSTCMP2)MSTCMP2 0 (MSTCMP3)MSTCMP3 0 (MSTCMP4)MSTCMP4 0 (TIMEVNT1)TIMEVNT1 0 (TIMEVNT2)TIMEVNT2 0 (TIMEVNT3)TIMEVNT3 0 (TIMEVNT4)TIMEVNT4 0 (TIMEVNT5)TIMEVNT5 0 (TIMEVNT6)TIMEVNT6 0 (TIMEVNT7)TIMEVNT7 0 (TIMEVNT8)TIMEVNT8 0 (TIMEVNT9)TIMEVNT9 0 (EXTEVNT1)EXTEVNT1 0 (EXTEVNT2)EXTEVNT2 0 (EXTEVNT3)EXTEVNT3 0 (EXTEVNT4)EXTEVNT4 0 (EXTEVNT5)EXTEVNT5 0 (EXTEVNT6)EXTEVNT6 0 (EXTEVNT7)EXTEVNT7 0 (EXTEVNT8)EXTEVNT8 0 (EXTEVNT9)EXTEVNT9 0 (EXTEVNT10)EXTEVNT10 0 (UPDATE)UPDATE

Description

Timerx Output1 Set Register

Fields

SST

Software Set trigger

RESYNC

Timer A resynchronizaton

PER

Timer A Period

CMP1

Timer A compare 1

CMP2

Timer A compare 2

CMP3

Timer A compare 3

CMP4

Timer A compare 4

MSTPER

Master Period

MSTCMP1

Master Compare 1

MSTCMP2

Master Compare 2

MSTCMP3

Master Compare 3

MSTCMP4

Master Compare 4

TIMEVNT1

Timer Event 1

TIMEVNT2

Timer Event 2

TIMEVNT3

Timer Event 3

TIMEVNT4

Timer Event 4

TIMEVNT5

Timer Event 5

TIMEVNT6

Timer Event 6

TIMEVNT7

Timer Event 7

TIMEVNT8

Timer Event 8

TIMEVNT9

Timer Event 9

EXTEVNT1

External Event 1

EXTEVNT2

External Event 2

EXTEVNT3

External Event 3

EXTEVNT4

External Event 4

EXTEVNT5

External Event 5

EXTEVNT6

External Event 6

EXTEVNT7

External Event 7

EXTEVNT8

External Event 8

EXTEVNT9

External Event 9

EXTEVNT10

External Event 10

UPDATE

Registers update (transfer preload to active)

Links

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