RCC_APB1SMENR2

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Interpret as RCC_APB1SMENR2

LPUART1SMEN=B_0x0, UCPD1SMEN=B_0x0, I2C4SMEN=B_0x0

APB1 peripheral clocks enable in Sleep and Stop modes register 2

LPUART1SMEN	Low power UART 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): LPUART1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): LPUART1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
I2C4SMEN	I2C4 clocks enable during Sleep and Stop modes Set and cleared by software 0 (B_0x0): I2C4 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C4 clock enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
UCPD1SMEN	UCPD1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): UCPD1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): UCPD1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes

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