SPI4EN=B_0x0, TIM1EN=B_0x0, TIM16EN=B_0x0, HRTIM1EN=B_0x0, TIM8EN=B_0x0, SAI1EN=B_0x0, TIM15EN=B_0x0, TIM20EN=B_0x0, SPI1EN=B_0x0, USART1EN=B_0x0, SYSCFGEN=B_0x0, TIM17EN=B_0x0
APB2 peripheral clock enable register
| SYSCFGEN | SYSCFG + COMP + VREFBUF + OPAMP clock enable Set and cleared by software. 0 (B_0x0): SYSCFG + COMP + VREFBUF + OPAMP clock disabled 1 (B_0x1): SYSCFG + COMP + VREFBUF + OPAMP clock enabled |
| TIM1EN | TIM1 timer clock enable Set and cleared by software. 0 (B_0x0): TIM1 timer clock disabled 1 (B_0x1): TIM1P timer clock enabled |
| SPI1EN | SPI1 clock enable Set and cleared by software. 0 (B_0x0): SPI1 clock disabled 1 (B_0x1): SPI1 clock enabled |
| TIM8EN | TIM8 timer clock enable Set and cleared by software. 0 (B_0x0): TIM8 timer clock disabled 1 (B_0x1): TIM8 timer clock enabled |
| USART1EN | USART1clock enable Set and cleared by software. 0 (B_0x0): USART1clock disabled 1 (B_0x1): USART1clock enabled |
| SPI4EN | SPI4 clock enable Set and cleared by software. 0 (B_0x0): SPI4 clock disabled 1 (B_0x1): SPI4 clock enabled |
| TIM15EN | TIM15 timer clock enable Set and cleared by software. 0 (B_0x0): TIM15 timer clock disabled 1 (B_0x1): TIM15 timer clock enabled |
| TIM16EN | TIM16 timer clock enable Set and cleared by software. 0 (B_0x0): TIM16 timer clock disabled 1 (B_0x1): TIM16 timer clock enabled |
| TIM17EN | TIM17 timer clock enable Set and cleared by software. 0 (B_0x0): TIM17 timer clock disabled 1 (B_0x1): TIM17 timer clock enabled |
| TIM20EN | TIM20 timer clock enable Set and cleared by software. 0 (B_0x0): TIM20 clock disabled 1 (B_0x1): TIM20 clock enabled |
| SAI1EN | SAI1 clock enable Set and cleared by software. 0 (B_0x0): SAI1 clock disabled 1 (B_0x1): SAI1 clock enabled |
| HRTIM1EN | HRTIM1 clock enable Set and cleared by software. 0 (B_0x0): HRTIM1 clock disabled 1 (B_0x1): HRTIM1 clock enable |