PVDLS=B_0x0, PVMEN2=B_0x0, PVMEN1=B_0x0, PVDE=B_0x0
Power control register 2
| PVDE | Programmable voltage detector enable Note: This bit is write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. 0 (B_0x0): Programmable voltage detector disable. 1 (B_0x1): Programmable voltage detector enable. |
| PVDLS | Programmable voltage detector level selection. These bits select the PVD falling threshold: Note: These bits are write-protected when the PVDL bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset. 0 (B_0x0): VPVD0 PVD threshold 0 1 (B_0x1): VPVD1 PVD threshold 1 2 (B_0x2): VPVD2 PVD threshold 2 3 (B_0x3): VPVD3 PVD threshold 3 4 (B_0x4): VPVD4 PVD threshold 4 5 (B_0x5): VPVD5 PVD threshold 5 6 (B_0x6): VPVD6 PVD threshold 6 7 (B_0x7): External input analog voltage PVD_IN (compared internally to VREFINT) |
| PVMEN1 | Peripheral voltage monitoring 3 enable: VDDA vs. ADC/COMP min voltage 1.62V 0 (B_0x0): PVM1 (VDDA monitoring vs. 1.62V threshold) disable. 1 (B_0x1): PVM1 (VDDA monitoring vs. 1.62V threshold) enable. |
| PVMEN2 | Peripheral voltage monitoring 4 enable: VDDA vs. DAC 1MSPS /DAC 15MSPS min voltage. 0 (B_0x0): PVM2 (VDDA monitoring vs. 1.8 V threshold) disable. 1 (B_0x1): PVM2 (VDDA monitoring vs. 1.8 V threshold) enable. |