STMicroelectronics /STM32G491xx /RCC /RCC_AHB1ENR

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Interpret as RCC_AHB1ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DMA1EN 0 (B_0x0)DMA2EN 0 (B_0x0)DMAMUX1EN 0 (B_0x0)CORDICEN 0 (B_0x0)FMACEN 0 (B_0x0)FLASHEN 0 (B_0x0)CRCEN

CORDICEN=B_0x0, CRCEN=B_0x0, FMACEN=B_0x0, FLASHEN=B_0x0, DMAMUX1EN=B_0x0, DMA2EN=B_0x0, DMA1EN=B_0x0

Description

AHB1 peripheral clock enable register

Fields

DMA1EN

DMA1 clock enable Set and cleared by software.

0 (B_0x0): DMA1 clock disable

1 (B_0x1): DMA1 clock enable

DMA2EN

DMA2 clock enable Set and cleared by software.

0 (B_0x0): DMA2 clock disable

1 (B_0x1): DMA2 clock enable

DMAMUX1EN

DMAMUX1 clock enable Set and reset by software.

0 (B_0x0): DMAMUX1 clock disabled

1 (B_0x1): DMAMUX1 clock enabled

CORDICEN

CORDIC clock enable Set and reset by software.

0 (B_0x0): CORDIC clock disabled

1 (B_0x1): CORDIC clock enabled

FMACEN

FMAC enable Set and reset by software.

0 (B_0x0): FMAC clock disabled

1 (B_0x1): FMAC clock enabled

FLASHEN

Flash memory interface clock enable Set and cleared by software. This bit can be disabled only when the Flash is in power down mode.

0 (B_0x0): Flash memory interface clock disable

1 (B_0x1): Flash memory interface clock enable

CRCEN

CRC clock enable Set and cleared by software.

0 (B_0x0): CRC clock disable

1 (B_0x1): CRC clock enable

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