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STMicroelectronics /STM32G491xx /RCC /RCC_AHB1RSTR

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Interpret as RCC_AHB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DMA1RST 0 (B_0x0)DMA2RST 0 (B_0x0)DMAMUX1RST 0 (B_0x0)CORDICRST 0 (B_0x0)FMACRST 0 (B_0x0)FLASHRST 0 (B_0x0)CRCRST

CRCRST=B_0x0, FLASHRST=B_0x0, FMACRST=B_0x0, CORDICRST=B_0x0, DMA2RST=B_0x0, DMAMUX1RST=B_0x0, DMA1RST=B_0x0

Description

AHB1 peripheral reset register

Fields

DMA1RST

DMA1 reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset DMA1
DMA2RST

DMA2 reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset DMA2
DMAMUX1RST

Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset DMAMUX1
CORDICRST

Set and cleared by software

0 (B_0x0): No effect

1 (B_0x1): Reset CORDIC
FMACRST

Set and cleared by software

0 (B_0x0): No effect

1 (B_0x1): Reset FMAC
FLASHRST

Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode.

0 (B_0x0): No effect

1 (B_0x1): Reset Flash memory interface
CRCRST

CRC reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset CRC

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data