RegViz: Visualize RCC_AHB2SMENR Bitfield

STMicroelectronics /STM32G491xx /RCC /RCC_AHB2SMENR

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Interpret as RCC_AHB2SMENR

DAC3SMEN=B_0x0, DAC4SMEN=B_0x0, DAC1SMEN=B_0x0, SRAM2SMEN=B_0x0, GPIOASMEN=B_0x0, GPIOGSMEN=B_0x0, GPIOCSMEN=B_0x0, CCMSRAMSMEN=B_0x0, GPIOBSMEN=B_0x0, GPIOFSMEN=B_0x0, ADC12SMEN=B_0x0, AESSMEN=B_0x0, RNGEN=B_0x0, GPIOESMEN=B_0x0, GPIODSMEN=B_0x0, DAC2SMEN=B_0x0, ADC345SMEN=B_0x0

Description

AHB2 peripheral clocks enable in Sleep and Stop modes register

Fields

GPIOASMEN	IO port A clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port A clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port A clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
GPIOBSMEN	IO port B clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port B clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port B clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
GPIOCSMEN	IO port C clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port C clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port C clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
GPIODSMEN	IO port D clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port D clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port D clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
GPIOESMEN	IO port E clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port E clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port E clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
GPIOFSMEN	IO port F clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port F clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port F clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
GPIOGSMEN	IO port G clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): IO port G clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): IO port G clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
CCMSRAMSMEN	CCM SRAM interface clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): CCM SRAM interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): CCM SRAM interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SRAM2SMEN	SRAM2 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SRAM2 interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SRAM2 interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
ADC12SMEN	ADC12 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): ADC12 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ADC12 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
ADC345SMEN	ADC345 clock enable Set and cleared by software. 0 (B_0x0): ADC345 clock disabled 1 (B_0x1): ADC345 clock enabled
DAC1SMEN	DAC1 clock enable Set and cleared by software. 0 (B_0x0): DAC1 clock disabled 1 (B_0x1): DAC1 clock enabled during sleep and stop modes
DAC2SMEN	DAC2 clock enable Set and cleared by software. 0 (B_0x0): DAC2 clock disabled 1 (B_0x1): DAC2 clock enabled during sleep and stop modes
DAC3SMEN	DAC3 clock enable Set and cleared by software. 0 (B_0x0): DAC3 clock disabled 1 (B_0x1): DAC3 clock enabled during sleep and stop modes
DAC4SMEN	DAC4 clock enable Set and cleared by software. 0 (B_0x0): DAC4 clock disabled 1 (B_0x1): DAC4 clock enabled during sleep and stop modes
AESSMEN	AESM clocks enable Set and cleared by software. 0 (B_0x0): AESM clocks disabled 1 (B_0x1): AESM clocks enabled
RNGEN	RNG enable Set and cleared by software. 0 (B_0x0): RNG disabled 1 (B_0x1): RNG enabled

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