RegViz: Visualize RCC_APB1SMENR1 Bitfield

STMicroelectronics /STM32G491xx /RCC /RCC_APB1SMENR1

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Interpret as RCC_APB1SMENR1

SPI3SMEN=B_0x0, TIM2SMEN=B_0x0, USART2SMEN=B_0x0, I2C1SMEN=B_0x0, I2C3SMEN=B_0x0, TIM5SMEN=B_0x0, TIM3SMEN=B_0x0, USBSMEN=B_0x0, TIM7SMEN=B_0x0, LPTIM1SMEN=B_0x0, I2C2SMEN=B_0x0, UART5SMEN=B_0x0, SPI2SMEN=B_0x0, CRSSMEN=B_0x0, USART3SMEN=B_0x0, WWDGSMEN=B_0x0, TIM4SMEN=B_0x0, PWRSMEN=B_0x0, FDCANSMEN=B_0x0, RTCAPBSMEN=B_0x0, UART4SMEN=B_0x0, TIM6SMEN=B_0x0

Description

APB1 peripheral clocks enable in Sleep and Stop modes register 1

Fields

TIM2SMEN	TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM3SMEN	TIM3 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM4SMEN	TIM4 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM4 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM4 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM5SMEN	TIM5 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM5 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM5 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM6SMEN	TIM6 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM6 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM6 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
TIM7SMEN	TIM7 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): TIM7 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): TIM7 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
CRSSMEN	CRS timer clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): CRS clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): CRS clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
RTCAPBSMEN	RTC APB clock enable during Sleep and Stop modes Set and cleared by software 0 (B_0x0): RTC APB clock disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): RTC APB clock enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
WWDGSMEN	Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated. 0 (B_0x0): Window watchdog clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): Window watchdog clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SPI2SMEN	SPI2 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SPI2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SPI2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SPI3SMEN	SPI3 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SPI3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SPI3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
USART2SMEN	USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): USART2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): USART2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
USART3SMEN	USART3 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): USART3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): USART3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
UART4SMEN	UART4 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): UART4 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): UART4 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
UART5SMEN	UART5 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): UART5 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): UART5 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
I2C1SMEN	I2C1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): I2C1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): I2C1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
I2C2SMEN	I2C2 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): I2C2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): I2C2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
USBSMEN	USB device clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): USB device clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): USB device clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
FDCANSMEN	FDCAN clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): FDCAN clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): FDCAN clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
PWRSMEN	Power interface clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): Power interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): Power interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
I2C3SMEN	I2C3 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): I2C3 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): I2C3 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
LPTIM1SMEN	Low power timer 1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LPTIM1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes

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