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STMicroelectronics /STM32G491xx /RCC /RCC_CRRCR

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Interpret as RCC_CRRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HSI48ON 0 (B_0x0)HSI48RDY 0HSI48CAL

HSI48ON=B_0x0, HSI48RDY=B_0x0

Description

Clock recovery RC register

Fields

HSI48ON

HSI48 clock enable Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.

0 (B_0x0): HSI48 oscillator OFF

1 (B_0x1): HSI48 oscillator ON
HSI48RDY

HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.

0 (B_0x0): HSI48 oscillator not ready

1 (B_0x1): HSI48 oscillator ready
HSI48CAL

HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. They are ready only.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data