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STMicroelectronics /STM32G4A1xx /CRS /ICR

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Interpret as ICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNCOKC)SYNCOKC 0 (SYNCWARNC)SYNCWARNC 0 (ERRC)ERRC 0 (ESYNCC)ESYNCC

Description

CRS interrupt flag clear register

Fields

SYNCOKC

SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.
SYNCWARNC

SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
ERRC

Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register.
ESYNCC

Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data