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STMicroelectronics /STM32G4A1xx /DAC1 /DAC_SR

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Interpret as DAC_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DAC1RDY)DAC1RDY 0 (DORSTAT1)DORSTAT1 0 (DMAUDR1)DMAUDR1 0 (CAL_FLAG1)CAL_FLAG1 0 (BWST1)BWST1 0 (DAC2RDY)DAC2RDY 0 (DORSTAT2)DORSTAT2 0 (DMAUDR2)DMAUDR2 0 (CAL_FLAG2)CAL_FLAG2 0 (BWST2)BWST2

Description

DAC status register

Fields

DAC1RDY

DAC channel1 ready status bit
DORSTAT1

DAC channel1 output register status bit
DMAUDR1

DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
CAL_FLAG1

DAC Channel 1 calibration offset status This bit is set and cleared by hardware
BWST1

DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).
DAC2RDY

DAC channel 2 ready status bit
DORSTAT2

DAC channel 2 output register status bit
DMAUDR2

DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
CAL_FLAG2

DAC Channel 2 calibration offset status This bit is set and cleared by hardware
BWST2

DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data