STMicroelectronics /STM32G4A1xx /FDCAN /CKDIV

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Interpret as CKDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PDIV

Description

FDCAN CFG clock divider register

Fields

PDIV

input clock divider. the APB clock could be divided prior to be used by the CAN sub

Links

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