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STMicroelectronics /STM32G4A1xx /FLASH /ACR

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Interpret as ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LATENCY0 (PRFTEN)PRFTEN 0 (ICEN)ICEN 0 (DCEN)DCEN 0 (ICRST)ICRST 0 (DCRST)DCRST 0 (RUN_PD)RUN_PD 0 (SLEEP_PD)SLEEP_PD 0 (DBG_SWEN)DBG_SWEN

Description

Access control register

Fields

LATENCY

Latency
PRFTEN

Prefetch enable
ICEN

Instruction cache enable
DCEN

Data cache enable
ICRST

Instruction cache reset
DCRST

Data cache reset
RUN_PD

Flash Power-down mode during Low-power run mode
SLEEP_PD

Flash Power-down mode during Low-power sleep mode
DBG_SWEN

Debug software enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data