STMicroelectronics /STM32G4A1xx /RCC /RCC_PLLCFGR

Main PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC should be 00.

0 (B_0x0): No clock sent to PLL

1 (B_0x1): No clock sent to PLL

2 (B_0x2): HSI16 clock selected as PLL clock entry

3 (B_0x3): HSE clock selected as PLL clock entry

Division factor for the main PLL input clock Set and cleared by software to divide the PLL input clock before the VCO. These bits can be written only when all PLLs are disabled. VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 16 … Note: The software has to set these bits correctly to ensure that the VCO input frequency is within the range defined in the device datasheet.

0 (B_0x0): PLLM = 1

1 (B_0x1): PLLM = 2

2 (B_0x2): PLLM = 3

3 (B_0x3): PLLM = 4

4 (B_0x4): PLLM = 5

5 (B_0x5): PLLM = 6

6 (B_0x6): PLLM = 7

7 (B_0x7): PLLM = 8

8 (B_0x8): PLLSYSM = 9

15 (B_0xF): PLLSYSM= 16

Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127 … … Note: The software has to set correctly these bits to assure that the VCO output frequency is within the range defined in the device datasheet.

0 (B_0x0): PLLN = 0 wrong configuration

1 (B_0x1): PLLN = 1 wrong configuration

7 (B_0x7): PLLN = 7 wrong configuration

8 (B_0x8): PLLN = 8

9 (B_0x9): PLLN = 9

127 (B_0x7F): PLLN = 127

Main PLL PLL “P” clock output enable Set and reset by software to enable the PLL “P” clock output of the PLL. In order to save power, when the PLL “P” clock output of the PLL is not used, the value of PLLPEN should be 0.

0 (B_0x0): PLL “P” clock output disable

1 (B_0x1): PLL “P” clock output enable

Main PLL division factor for PLL “P” clock. Set and cleared by software to control the frequency of the main PLL output clock PLL “P” clock. These bits can be written only if PLL is disabled. When the PLLPDIV[4:0] is set to “00000”PLL “P” output clock frequency = VCO frequency / PLLP with PLLP =7, or 17 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain.

0 (B_0x0): PLLP = 7

1 (B_0x1): PLLP = 17

Main PLL “Q” clock output enable Set and reset by software to enable the PLL “Q” clock output of the PLL. In order to save power, when the PLL “Q” clock output of the PLL is not used, the value of PLLQEN should be 0.

0 (B_0x0): PLL “Q” clock output disable

1 (B_0x1): PLL “Q” clock output enable

Main PLL division factor for PLL “Q” clock. Set and cleared by software to control the frequency of the main PLL output clock PLL “Q” clock. This output can be selected for USB, RNG, SAI (48 MHz clock). These bits can be written only if PLL is disabled. PLL “Q” output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain.

0 (B_0x0): PLLQ = 2

1 (B_0x1): PLLQ = 4

2 (B_0x2): PLLQ = 6

3 (B_0x3): PLLQ = 8

PLL “R” clock output enable Set and reset by software to enable the PLL “R” clock output of the PLL (used as system clock). This bit cannot be written when PLL “R” clock output of the PLL is used as System Clock. In order to save power, when the PLL “R” clock output of the PLL is not used, the value of PLLREN should be 0.

0 (B_0x0): PLL “R” clock output disable

1 (B_0x1): PLL “R” clock output enable

Main PLL division factor for PLL “R” clock (system clock) Set and cleared by software to control the frequency of the main PLL output clock PLLCLK. This output can be selected as system clock. These bits can be written only if PLL is disabled. PLL “R” output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8 Note: The software has to set these bits correctly not to exceed 170 MHz on this domain.

0 (B_0x0): PLLR = 2

1 (B_0x1): PLLR = 4

2 (B_0x2): PLLR = 6

3 (B_0x3): PLLR = 8

Main PLLP division factor Set and cleared by software to control the PLL “P” frequency. PLL “P” output clock frequency = VCO frequency / PLLPDIV. …

0 (B_0x0): PLL “P” clock is controlled by the bit PLLP

1 (B_0x1): Reserved.

2 (B_0x2): PLL “P” clock = VCO / 2

31 (B_0x1F): PLL “P” clock = VCO / 31