FDCANEN=B_0x0, I2C1EN=B_0x0, LPTIM1EN=B_0x0, I2C2EN=B_0x0, UART4EN=B_0x0, I2C3EN=B_0x0, USART3EN=B_0x0, UART5EN=B_0x0, RTCAPBEN=B_0x0, TIM4EN=B_0x0, WWDGEN=B_0x0, PWREN=B_0x0, SPI2EN=B_0x0, USBEN=B_0x0, SPI3EN=B_0x0, CRSEN=B_0x0, USART2EN=B_0x0, TIM6EN=B_0x0, TIM5EN=B_0x0, TIM3EN=B_0x0, TIM7EN=B_0x0, TIM2EN=B_0x0
APB1 peripheral clock enable register 1
| TIM2EN | TIM2 timer clock enable Set and cleared by software. 0 (B_0x0): TIM2 clock disabled 1 (B_0x1): TIM2 clock enabled |
| TIM3EN | TIM3 timer clock enable Set and cleared by software. 0 (B_0x0): TIM3 clock disabled 1 (B_0x1): TIM3 clock enabled |
| TIM4EN | TIM4 timer clock enable Set and cleared by software. 0 (B_0x0): TIM4 clock disabled 1 (B_0x1): TIM4 clock enabled |
| TIM5EN | TIM5 timer clock enable Set and cleared by software. 0 (B_0x0): TIM5 clock disabled 1 (B_0x1): TIM5 clock enabled |
| TIM6EN | TIM6 timer clock enable Set and cleared by software. 0 (B_0x0): TIM6 clock disabled 1 (B_0x1): TIM6 clock enabled |
| TIM7EN | TIM7 timer clock enable Set and cleared by software. 0 (B_0x0): TIM7 clock disabled 1 (B_0x1): TIM7 clock enabled |
| CRSEN | CRS Recovery System clock enable Set and cleared by software. 0 (B_0x0): CRS clock disabled 1 (B_0x1): CRS clock enabled |
| RTCAPBEN | RTC APB clock enable Set and cleared by software 0 (B_0x0): RTC APB clock disabled 1 (B_0x1): RTC APB clock enabled |
| WWDGEN | Window watchdog clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 0 (B_0x0): Window watchdog clock disabled 1 (B_0x1): Window watchdog clock enabled |
| SPI2EN | SPI2 clock enable Set and cleared by software. 0 (B_0x0): SPI2 clock disabled 1 (B_0x1): SPI2 clock enabled |
| SPI3EN | SPI3 clock enable Set and cleared by software. 0 (B_0x0): SPI3 clock disabled 1 (B_0x1): SPI3 clock enabled |
| USART2EN | USART2 clock enable Set and cleared by software. 0 (B_0x0): USART2 clock disabled 1 (B_0x1): USART2 clock enabled |
| USART3EN | USART3 clock enable Set and cleared by software. 0 (B_0x0): USART3 clock disabled 1 (B_0x1): USART3 clock enabled |
| UART4EN | UART4 clock enable Set and cleared by software. 0 (B_0x0): UART4 clock disabled 1 (B_0x1): UART4 clock enabled |
| UART5EN | UART5 clock enable Set and cleared by software. 0 (B_0x0): UART5 clock disabled 1 (B_0x1): UART5 clock enabled |
| I2C1EN | I2C1 clock enable Set and cleared by software. 0 (B_0x0): I2C1 clock disabled 1 (B_0x1): I2C1 clock enabled |
| I2C2EN | I2C2 clock enable Set and cleared by software. 0 (B_0x0): I2C2 clock disabled 1 (B_0x1): I2C2 clock enabled |
| USBEN | USB device clock enable Set and cleared by software. 0 (B_0x0): USB device clock disabled 1 (B_0x1): USB device clock enabled |
| FDCANEN | FDCAN clock enable Set and cleared by software. 0 (B_0x0): FDCAN clock disabled 1 (B_0x1): FDCAN clock enabled |
| PWREN | Power interface clock enable Set and cleared by software. 0 (B_0x0): Power interface clock disabled 1 (B_0x1): Power interface clock enabled |
| I2C3EN | I2C3 clock enable Set and cleared by software. 0 (B_0x0): I2C3 clock disabled 1 (B_0x1): I2C3 clock enabled |
| LPTIM1EN | Low power timer 1 clock enable Set and cleared by software. 0 (B_0x0): LPTIM1 clock disabled 1 (B_0x1): LPTIM1 clock enabled |